Hysteresis limiter has been widely used in the electronic device. For instance, in a frequency shift keying (FSK) receiver, the input signal is first processed by a front end filter followed by a hysteresis limiter. The front end filter, in typical, is embodied by a switched capacitor filter which is well known to occupy a smaller chip area. On the other hand, the implementation of hysteresis limiter comes from the requirement of noise immunity.
In a typical switched capacitor filter, an operational amplifier is implemented which usually generates an output signal with offset voltage. Also in the hysteresis limiter, an operational amplifier or a comparator is implemented which also generates an output signal with an offset voltage. In the following recitation, the term "amplifier" includes both the operational amplifier and the comparator. As the hysteresis limiter is provided to process the signal from the switched capacitor filter, the limiter encounters offset voltage itself and offset voltage with the input signal that is outputted from the switched capacitor filter. When the system's overall offset voltage caused by the switched capacitor filter and hysteresis limiter is larger than the resolution of the hysteresis limiter, the device malfunctions.
As a result, some prior arts teach techniques tackling to offset error either of the hysteresis limiter or the switched capacitor filter. In U.S. Pat. No. 4,616,145, an offset cancellation technique, which subtracts the selected signal by the offset voltage of the comparator, is disclosed to reduce the output error of the comparator. However, the offset of the input signal itself can not be canceled by the disclosed technique. In U.S. Pat. No. 4,543,534, an offset compensated switched capacitor circuit is disclosed to reduce the offset error within the front end filter. However, it is found out that using single-ended circuit in U.S. Pat. No. 4,543,534 may still have output offset concern regarding the charge rejection noise inherent with the single-ended circuit. Implementing fully-differential circuit in U.S. Pat. No. 4,543,534 may increase the overall circuit area substantially. In U.S. Pat. No. 5,166,632, the limiter circuit disclosed stores the offset error associated with the hysteresis limiter. However, the technique disclosed needs large RC value which may not be implemented on an integrated circuit.
It is therefore the main object of the invention to provide an alternative and simple approach to overcome the offset voltages in associated with the input signal to hysteresis limiter and the hysteresis limiter itself.